Recent developments in semiconductor memory technology have substantially increased the use of semiconductor random access memories (RAMs) which usually are large scale integration (LSI) devices employing either bipolar or metal oxide semiconductor (MOS) techniques. A RAM system 10 shown schematically in FIG. 1 consists mainly of a number of memory devices 12, address decoders 14, and data buffer 16 connected on data and address buses 17, 19. Each memory device or chip 12 contains a number of memory cells organized in words and capable of being writen into as well as read from. Read/write (R/W) signals are applied to the RAM devices 12 through control bus 21.
Physical faults, which can occur in any part of the memory chip, depend on such factors as component density, circuit layout and method of manufacture. Test procedures necessary to detect these faults are classified into three classes, DC parametric testing, AC parametric testing and functional testing.
In DC parametric testing, DC parameters in the chip are checked for unacceptable output levels, high power consumption, fanout capability, noise margins, rise and fall times of logical signals and other factors. AC parametric testing, or dynamic testing, measures AC parameters, such as memory access time, set up time, and hold time, to detect any malfunction. Examples of malfunctions that can be detected by AC testing include "slow write-recovery" where the memory does not produce the correct information at the specified access time when each read cycle is preceded by a write cycle, and "sleeping sickness" where the memory loses information in less than the specified hold time.
Functional testing detects permanent faults that cause the memory to function incorrectly. Generally, a read/write RAM can be defined as functional or operative if the value read from any cell matches the value most recently written to that cell, and does not depend on the value written to, or the contents of any other cells.
A functional test that will cover all the possible faults is impractical since the complexity of such a test will be on the order of 2.sup.n, where n is the number of cells in the memory. This is because each cell for all possible states of the remaining cells must be monitored during a measurement cycle. Thus, to test a 1 kilobit RAM, assuming a cell access time of 500 nanoseconds, would require approximately 10.sup.293 seconds. To develop any practically feasible test procedure, therefore, the test must be concerned not with all possible faults but only with the subset of faults that is most likely to occur. This is known as fault modeling.
The model upon which the test in accordance with the invention is based assumes very little about the layout of the chips under test, or even about which address lines select chips and which select bits within chips. The model is based on a hierarchy of memory devices, beginning at the lowest level with cells within a chip. The next level is the chips per se, followed by a board of chips. The highest level is the complete system under test. Each level of the hierarchy has associated with it a subset of address bits that select among its constituent components. Levels of the hierarchy are organized into rows and columns, with separate address bits controlling each. The model includes memory systems organized into words. At the upper levels of the hierarchy, it is typical for a full word to reside in a component, i.e., a board will usually contain a full word. For example, a system with 16 bit words consisting of one or more boards with a number of 16K.times.1 chips has all the bits on each board, but there is a separate chip for each bit of the word. On the other hand, a system could be constructed from 2K.times.8 chips, having 8 different data bits on each chip.
The model includes the following faults:
1. Stuck RAM cells. This occurs when a cell is always either a 1 or a 0. In one type, a cell might power up in some state, and be capable of being read, but once transitioned to the opposite state, cannot be further changed. In another type, known as a transition fault, the cell appears stuck-at relative to write operations addresses to it, but might still be changed due to a simultaneously occurring coupling fault. PA1 2. Stuck address bits. This fault maps two sets of addresses together. If the fault is at a level in the hierarchy where each component contains a full word, all bits of the words will be affected. PA1 3. Faulty decoder. Here, a row or column decoder either fails to select when it should or selects when it should not. The first case will result in a read returning 0s or 1s, depending upon the memory design, while writes will be ineffective. Multiple selection causes writes to affect memory cells. At levels higher than the chip level, multiple selection during a read will non-destructively AND or OR multiple cells depending upon the memory design. The same may be true for multiple column selection at the chip level, depending on the design of the particular memory chip. If multiple rows in a chip are selected and the affected cells do not all contain the same value, a read will return an undetermined value and the affected cells will be set to that value. This fault will also cause the data to be destroyed during refresh cycles. PA1 4. Stuck data register bit. This fault causes the same bit of all words in the affected component of the memory system to appear stuck. PA1 5. Shorted or pattern sensitive data register bits. Here, it is impossible to write words with some particular pattern in some set of data bits, and affects all subordinate components in the memory hierarchy. PA1 6. Static coupling faults. In this fault type, two cells are coupled to each other such that one or more of the four possible states of the cells are prohibited. A special case is aliasing, in which the 01 and 10 states are prohibited. In addition, a write to a cell always succeeds, affecting other cells as well. Inverted aliasing is always possible, wherein the prohibited states are 00 and 11. In a static memory wherein cells are built from flipflops, this could arise from coupling between the true side of one flipflop and the false side of a neighboring flipflop. Coupling faults must be within cells of the same chip. PA1 7. Dynamic coupling faults. Herein, the setting of one cell may change, either setting or clearing, some other cell. This need not be symmetric. PA1 8. Pattern sensitive faults. This type of fault makes it impossible to write some pattern into a group of adjacent cells. PA1 9. Address to data shorts. This type of fault appears as either stuck data bits, when the address line overwhelms the data line, or as dynamic coupling to some other address, when the data line overwhelms the address line. PA1 10. Shorts between address or data lines and the R/W line. Herein, if a data or address is forced to the wrong state, a stuck address bit or a stuck data register bit will appear. If the R/W line is forced to a write when a read is requested, the memory does not return a value, and the value read wll be some fixed value (typically all 1s or all 0s) depending on the construction of the memory system.
In a Galpat test, into a background of 0s, the first cell (test cell) is complemented and then read alternately with every other cell in memory. The sequence continues as every memory cell eventually becomes the test cell. The system then executes the same sequence using complemented data. Galpat has an execution time proportional to the square of the cell count, but misses many faults.
A march test is one that sequences through a set of addresses doing the same thing at each address. In one type of standard march test, after writing a background of 0s to memory, the system reads the data at the first address and writes a 1 therein. The same two-step read/write procedure continues at each sequential cell until the system reaches the end of memory; each cell is then tested and changed back to 0 in reverse order until the system returns to the first address. Finally, the test is repeated using complemented data. In another type of march test, rather than writing the same bit into all cells, a fixed pattern of bits derived by applying a hash function to the address is written successively into the cells.
Any march test of either type that does exhaustive testing for coupling faults, including asymmetric and inverted coupling, in a 1.times.n memory that is assumed to have no transition faults, stuck-at faults or multiple access decoding faults, however, requires at least 14n operations. See Suk and Reddy, IEEE Transactions On Computers, Vol. C-30, No. 12, December 1981, pp. 982-985.
Decoder faults are manifest as coupling faults between corresponding cells in the affected rows. A standard march test of any order, using the same value at all addresses, will miss all faults of a given class on the affected row if it misses any of that class. Using a fixed sequence can improve such an algorithm by increasing the likelihood that corresponding cells are exercised in all possible combinations. For example, in a fixed sequence RAM short test used in the 9000 series instrumentation manufactured by John Fluke Mfg. Co., a sweep is made up the memory writing a value to each word location. In a second sweep, the value is compared to an expected value. The value written at each location is obtained by folding the address into a word which is the width of the data bus, and complementing and rotating the folded word if the address has odd parity. The bits of the resulting word depend approximately equally on every bit of the address, making the test suitable to detect aliasing caused by a short on any address line leading to the decoder, and affecting any data bit. Nevertheless, the set of combinations used is fixed by the sequence. While there may exist a sequence that will find decoder faults for a particular memory configuration, it is possible to construct a configuration that renders any given sequence ineffective.
Let TUk denote the operation of toggling a memory location k times, beginning with an up (0 to 1) transition, and TDk denote the corresponding thing starting with a down transition; a T without a following U or D designates a first transition that may be either up or down. Suk and Reddy show that any such test must contain the following. Going up (in addresses) RTUk.sub.1 (k.sub.1 .gtoreq.2) going up RTDk.sub.2 (k.sub.2 .gtoreq.2), going down RTUk.sub.3 (k.sub.3 .gtoreq.2), going down RTDk.sub.4 (k.sub.4 .gtoreq.2). Furthermore, either k.sub.1 &gt;2 or k.sub.2 &gt;2 or another sequence of the form going up RTk.sub.5 (k.sub.5 odd) must appear. Similarly, k.sub.3 &gt;2 or k.sub.4 &gt;2 or a sequence of the form going down RTk.sub.6 (k.sub.6 odd) must appear.
Suk and Reddy propose a 14N test, called Test A, that will find all stuck-at faults, transition faults, and multiple access decoding faults or all coupling faults. It assumes that the memory is initialized to all 0s, and contains the following sequences: going up RWcWcWc, going up RWcWc, going down RWcWcWc, going down RWcWc. Any march test of order less than 14n, however, will not detect all isolated coupling faults.
Suk and Reddy further propose a 16N test, called Test B, that finds all combinations of stuck-at faults, transition faults and coupling faults if no multiple access decoding faults are present. Test B consists of the following sequences: going up RWcRWcRWc, going up RWcWc, going down RWcWcWc, going down RWcWc. This test, preceded by a pass to intialize the memory to 0s, probably finds all combinations of stuck-at faults, transition faults, coupling faults and multiple access decoder faults.
A 30N test, developed by Nair, Thatte and Abraham, has the following sequences, where W0 and W1 indicate a write 0 and 1, respectively: going up W0, going up RW1, going down R, going up RW0, going down R, going down RW1, going up R, going down RW0, going up R, going up RW1W0, going down R, going down WR1W0, going up R, going up W1, going up WR0W1, going down R, going down RW0W1, going up R.
The above and other types of tests are summarized in Abadair and Reghbati, Functional Testing of Semiconductor Random Access Memories, Computing Surveys, Vol. 15, No. 3, September 1983, pp. 175-198.
Each of the aforementioned tests, as well as of others of which I am aware, requires a testing time that is impracticably long or else is unreliable because it tends to miss faults or certain classes of faults.
A primary object of the invention, is to provide functional testing of random access memories in as short a time as possible while identifying the most common faults, i.e., stuck data cells, defective decoders, defective address or data registers and faults between address and data lines.
Another object of the invention, is to provide a method of and system for testing memory faults in a random access memory, with a high probability of identifying coupling faults and decoder faults, all of which affect a number of different addresses.
A further object of the invention is to provide a method of and system for maximizing the likelihood of identifying memory faults using a memory test algorithm that requires as short a testing time as possible.